Program

FDL (loading) Program

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Dates

Main Conference

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Summer School

Pre-conference

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Program

The full program for FDL 2026 will be announced soon.

Check back here for the technical sessions, additional keynotes, and social events schedule.

Conference dates: (loading). Summer School: (loading).

Keynotes

Keynote 1

seL4: the journey of a verified kernel deployed in real systems

Abstract

With formal proofs of its correctness and security, seL4 provides the strongest assurance and isolation between untrusted and trusted components running in critical software systems, demonstrably preventing cyber attacks from endangering critical functionality and from propagating further. seL4 is being adopted in a number of sectors, from automotive to IoT, Defense, and more. The open-source seL4 Foundation provides the underlying support for its growing ecosystem of developers, contributors and adopters, and Proofcraft keeps pushing the roadmap of seL4's verification to make its formal proofs apply to more platforms, more features, and more properties. The talk will give an overview of seL4's journey and roadmap ahead.

Speaker Bio

June Andronick is CEO and co-founder of Proofcraft, a company providing commercial support for software verification in general and the seL4 microkernel verification in particular. She is also CEO of the seL4 Foundation, supporting the technology and community of seL4 users, adopters and developers. June has extensive leadership experience towards making the vision of verified software a reality in mainstream critical software. She was previously leading the Trustworthy Systems group, and contributed to the original seL4 verification. She holds a PhD in Computer Science from the University of Paris-Sud, France.

Keynote 2

From Models to Decisions - Why Modeling Must Become an Execution Engine in the Age of AI

Abstract

The role of modeling is undergoing a fundamental shift. Traditionally, models have been used to document, specify, and communicate complex systems. However, in an era increasingly shaped by artificial intelligence, distributed systems, and rapidly evolving requirements, this is no longer sufficient.

This keynote argues that modeling must evolve from a descriptive discipline into an execution-driven capability. Instead of creating models that merely represent systems, we need models that actively shape decisions, enable automation, and provide structure for AI-driven reasoning.

Drawing on real-world experience from enterprise architecture, model-based systems engineering (MBSE), and large-scale industrial deployments, this talk explores:

  • Why traditional modeling approaches are losing relevance in modern engineering environments
  • How AI changes the expectations towards structure, semantics, and traceability
  • What it takes to turn models into actionable assets across the lifecycle
  • How modeling can bridge the gap between engineering rigor and business impact

The keynote challenges the audience to rethink modeling not as an artifact, but as a strategic capability - one that enables organizations to manage complexity, increase resilience, and unlock the full potential of AI-assisted engineering.

Speaker Bio

Peter Lieber is a software entrepreneur and business developer with over 20 years of experience in model-based engineering and enterprise architecture. He plays a key role in building and scaling the European ecosystem around Sparx Systems, one of the world's leading platforms for modeling and architecture. His work focuses on bridging the gap between engineering methodologies and real-world business impact, particularly in domains such as MBSE, enterprise architecture, and AI-supported system design.

In addition to his work in the software industry, he is also active as an entrepreneur in sustainable retail and serves as president of the Austrian Gewerbeverein, representing SMEs and entrepreneurial interests. Peter is known for combining deep technical understanding with a pragmatic, business-driven perspective on modeling and digital transformation.

Keynote 3

Re engineering EDA in the Era of Pervasive Intelligence

Abstract

The rapid growth of system complexity - driven by AI workloads, heterogeneity, and aggressive technology scaling - is challenging traditional approaches to design and specification. While design and specification languages remain essential, productivity is increasingly limited by the ability to explore large design spaces, connect abstraction levels, and close design and verification loops efficiently.

This keynote presents an industrial perspective on how AI-powered and agentic EDA technologies are reshaping design flows for complex hardware and cyber-physical systems. By tightly integrating generative and agentic AI with existing languages, models, and signoff-grade tools, engineers can move from point automation to closed-loop, tool-in-the-loop workflows spanning specification, RTL design, verification, optimization, and debug.

Through concrete examples, the talk illustrates how AI agents augment - not replace - formal methods and design languages, enabling scalable, trustworthy co-design and pointing toward future evolutions of design and specification ecosystems.

Speaker Bio

Gianvito Lorusso is Senior Director of Project and Program Management at Synopsys, where he leads global, multi-site programs in the semiconductor and EDA domain, coordinating hundreds of engineers across advanced technology nodes. With more than 25 years of experience spanning ASIC design, verification, physical implementation, and large-scale SoC programs, he has worked across the full spectrum from hands-on engineering to strategic leadership.

Throughout his career at Synopsys, Cadence, and semiconductor design service companies, he has managed complex industrial projects for leading hyperscalers and semiconductor companies, including high-performance, automotive-grade, and AI-driven systems. His current focus includes the integration of AI and agentic technologies into EDA workflows, and the evolution of design and verification methodologies for increasingly complex systems.

Gianvito holds an M.Sc. in Electronic Engineering and is a PMP-certified professional.

Panel

Panel 1

The Virtual Prototype (VP) is Dead – Why do we invest so much effort in something that is rarely used

Panelists

Panelist Affiliation Email
Prof. Rainer Doemer University of California doemer@uci.edu
Prof. Franco Fummi University of Verona franco.fummi@univr.it
Eyck Jentsch Minres eyck@minres.com
Prof. Wolfgang Müller Universität Paderborn wmueller@hni.uni-paderborn.de
Dr. Jan-Hendrik Oetjens Robert Bosch GmbH jan-hendrik.oetjens@de.bosch.com

Special Session

Special Session 1

Hardware Construction Languages: Register Transfer Level on Steroids

Abstract

The 80's have seen the substitution of schematics by languages to describe digital circuits. Since then, standardization has gone its way, and current tools allow very efficient digital circuits to be produced from textual descriptions. Nevertheless, with growing circuit complexity, higher abstractions have been searched for while keeping full control over the produced circuits. Using languages at first designed for software, many hacks, more or less formalized, have been developed as code generators. With time, the need for a more formalized approach has emerged, as has the Hardware Construction Language community. This Special Session aims at gathering language designers and power users of these languages to discuss the current state and possible evolutions.

Accepted Papers

The following papers have been accepted for presentation at FDL (loading).

Authors Title
Lennart Weingarten, Kamalika Datta and Rolf Drechsler Scalable Verification for Dot-Product Architectures using Symbolic Computer Algebra
Yasmine Abu-Haeyeh, Tobias Ladner, Matthias Althoff and Lars Hedrich Formally Verifying Analog Neural Networks Under Process Variations Using Polynomial Zonotopes
Jan Kleinekathöfer, Lennart Weingarten, Kamalika Datta and Rolf Drechsler Polynomial Formal Verification of Structurally Simple Multipliers
Sallar Ahmadi-Pour, Luca Müller and Rolf Drechsler Exploring the Parameter Space for Constrained Random Verification of RISC-V CPUs
Loïc Sylvestre Hardware synthesis of functional programs with Esterel constructs
Sebastian Post, Hagen Heermann and Christoph Grimm Modeling Neural Networks in SysML v2: Introducing Performance Constraints in OpenBoardnet
Zayah Cortright, Prateek Ganguli, Tingan Zhu and Samarjit Chakraborty NAS-in-the-Loop: Trajectory-driven Neural Architecture Search for Safe Autonomous CPS
Milan Funck, Christoph Lüth and Rolf Drechsler FormalHandshake — Open Source Design and Verification Flow for complex Hardware Circuits
Maksym Labzhaniia, Julien Deantoni, Marie-Agnès Peraldi-Frati and Frédéric Mallet MakSafe: A Spatiotemporal Semantic Framework for Formal Specification and Compliance Checking of Road Vehicle Safety Rules
Andrei Mihai Albu and Sara Vinco SAMpLE: A SystemC-AMS Machine LEarning-based Framework for Virtual Prototyping
Katharina Ruep, Manfred Schlägl and Daniel Grosse FP-RVVTS: Sail-guided Verification of RISC-V Floating-Point Implementations
Byeonggil Jun, Deeksha Prahlad, Mehdi Ghasemi and Hokeun Kim Embodied AI Launcher: A Tool for Modeling, Simulation, and Deployment Evaluation of Transformer-Based Embodied AI Tasks at the Edge
Bhavay Arora, Rainer Dorsch and Christian Haubelt Enabling Cross-Language and Cross-Level Verification Reuse Using SCVPI*
Daniel Sarsur, Patrícia Nascimento Pena, Lucas Alves, Martijn Goorden and Michel Reniers Simultaneous Topology and Control Exploration for Manufacturing Systems
Anton Paule, Robert Kunzelmann, Markus Leibl, Johannes Geier, Stefan Wallentowitz, Wolfgang Ecker and Ulf Schlichtmann FITS: Towards Automatic Open-Source IP Integration
William Gaudelier, Dumitru Potop Butucaru and Albert Cohen Relaxed activation analysis of dataflow networks: A clock calculus for machine learning
Rainer Doemer A Breath of Fresh AIR: Programmatic Construction for SystemC
Edoardo Trombotto, Valentino Peluso, Andrea Calimera and Enrico Macii LLM-Guided Design Space Exploration for Neural Network Accelerators on FPGA
Uzair Khan, Luigi Capogrosso, Michele Magno, Franco Fummi and Marco Cristani TIPSter: Zero-Shot Anomaly Detection via Language-Steered Anomaly Informed Patches
Pavlo Tokariev and Julien Deantoni Refining Timing Uncertainty from Logical Time Specification to Operation
Oliver Bringmann and Samarjit Chakraborty From DNN Perception Accuracy to Physical Safety: ML/Architecture Co-Design for Autonomous CPS