FDL Summer School (loading)

Abstract

As hardware systems continue to grow in complexity, the languages used to describe them must evolve accordingly. Raising the level of abstraction in hardware design is essential to improve productivity, reuse, and design quality. This talk introduces hardware design languages from traditional HDLs to newer DSL-based approaches.

It presents the role of HDLs and DSLs in hardware development, highlighting the conceptual difference between software programming in C and hardware description, and examines the usability challenges of conventional RTL-centric design based on Verilog and SystemVerilog. High-Level Synthesis is discussed as an important step toward higher abstraction, while also showing why algorithmic descriptions alone are not sufficient for all hardware design tasks.

The session then introduces hardware DSLs such as Bluespec, Chisel, SpinalHDL, and Clash, focusing on the ideas that motivated their emergence and the abstractions they provide for hardware construction. It closes by exploring their relevance in the RISC-V ecosystem, where configurable architectures, reusable generators, and open design methodologies are increasingly important.

Abstract

This talk covers guiding principles of models and argues that abstraction is their most important feature. Because abstraction removes details, models are necessarily imperfect in some circumstances, echoing the observation that all models are wrong, but some are useful.

The session discusses several digital design abstraction methods, including lumped, value-discrete, and time-discrete models. It relates these abstractions to pre-clustered elements such as transistors, gates, registers, and transfer functions.

It further compares abstraction levels, connects them to current IP-based design, and shows how other disciplines, such as synchronous analog design or asynchronous digital design, fit into the broader abstraction scheme.

Abstract

This session explores SysML v2 from a meta-model perspective. It first contrasts the UML-based profile of SysML v1 with the KerML-based foundation of SysML v2.

After introducing both graphical and textual notations, the talk provides practical examples of the textual syntax together with the underlying grammar rules.

It concludes by examining extensibility and modularity mechanisms, showing how domain-specific adaptations can be defined with libraries and specializations without compromising core semantics.

Abstract

This hands-on tutorial introduces the Lingua Franca coordination language for modeling and programming time-sensitive systems with deterministic concurrency. Its primary goal is to give participants an engaging programming experience that helps them design domain-specific applications and systems with determinism and repeatability.

The tutorial includes a brief introduction to Lingua Franca, a live demo of building programs with specified timed behavior, and interactive programming exercises based on template code. It explores design alternatives for time-sensitive systems using the reactor model of computation, along with different coordination modes for federated and distributed Lingua Franca programs.

Participants will experience the full toolchain from code generation and compilation to distributed execution, reason about deterministic ordering mechanisms for timestamped events, and study trade-offs between consistency and availability in distributed concurrent settings.

Hands-on preparation instructions

Abstract

This hands-on tutorial introduces the GLACIER project, an open-source framework for the design, simulation, and validation of modern manufacturing systems. It starts from the challenges posed by increasingly complex cyber-physical production environments, including the integration of heterogeneous machines, software services, and communication infrastructures in service-oriented manufacturing architectures.

The session presents GLACIER as a framework for building open and extensible virtual testbeds in which advanced manufacturing software can be developed and evaluated before deployment. Particular attention is given to Frost, the GLACIER simulation platform built on Lingua Franca, which supports deterministic execution and unified modeling of machines, clients, data models, and communication behaviors.

Through guided practical activities, participants will explore how manufacturing components can be represented, connected, and executed in simulation, and how these virtual setups support early software validation, digital twin development, and machine-in-the-loop experimentation.

Hands-on preparation instructions

Abstract

This two-hour hands-on lab complements Daniele’s course on higher-level hardware abstractions by diving directly into the Chisel hardware construction language.

Phase 1: Foundations without the Friction
While Chisel operates at the Register Transfer Level (RTL), its Scala-based syntax offers a fresh perspective on digital design. We will begin by grounding ourselves in the essentials: defining circuits, modules, ports, signals, and registers. We’ll treat the initial syntax hurdle as a rite of passage—a quick investment that unlocks the true power of the language.

Phase 2: From “The Old Way” to Scalable Generators
The real magic of Chisel lies in its ability to be highly generic. We will move beyond static designs, starting with a traditional “fixed” circuit and evolving it into a reusable, parameterized generator. You’ll see firsthand how Chisel constructs can simplify a designer’s life, making hardware components adaptable to a wide variety of contexts and constraints.

Logistics: Zero-Setup Execution
Modern RTL generation and testing often come with complex tooling requirements. To ensure we spend our time designing rather than debugging environments, we will provide a pre-configured Docker image and a suite of automation scripts. This setup ensures a smooth, “plug-and-play” experience for all attendees on Linux.

Hands-on preparation instructions